5年以上
碩士
最近更新
2641人關(guān)注
職位描述
該職位還未進行加V認證，請仔細了解后再進行投遞！
職位描述：
1. high speed channel design, characterization, optimization, and correlation
2. parallel buses, ddr3/4 etc., timing and signal quality design and analysis
3. pdn dc drop and ac design and analysis, including decoupling capacitors selection and placement, also power plane optimization1. 1. master degree or above. 5+ years of experience in signal integrity design and verification, including 2+ years in system level
2. deep knowledge on transmission line theory, electromagnetic field theory and time & frequency domain analysis.
3. experiences with high speed digital board design.
4. experiences with major si/pi tools: cadence allegro, hyperlynx, sisoft, sigrity, ads, hfss, cst etc..
5. lab measurement experience with oscilloscopes, spectrum analyzers and vnas.
1. high speed channel design, characterization, optimization, and correlation
2. parallel buses, ddr3/4 etc., timing and signal quality design and analysis
3. pdn dc drop and ac design and analysis, including decoupling capacitors selection and placement, also power plane optimization1. 1. master degree or above. 5+ years of experience in signal integrity design and verification, including 2+ years in system level
2. deep knowledge on transmission line theory, electromagnetic field theory and time & frequency domain analysis.
3. experiences with high speed digital board design.
4. experiences with major si/pi tools: cadence allegro, hyperlynx, sisoft, sigrity, ads, hfss, cst etc..
5. lab measurement experience with oscilloscopes, spectrum analyzers and vnas.
注：聯(lián)系我時，請說是在四川人才網(wǎng)上看到的。
工作地點
地址：大連甘井子區(qū)北京-朝陽區(qū)
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詳細位置，可以參考上方地址信息
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職位發(fā)布者
HR
大連檸檬信息技術(shù)有限公司
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計算機軟件
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21-50人
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公司性質(zhì)未知
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數(shù)碼廣場軟件園8號樓
